957 lines
30 KiB
C
957 lines
30 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* QorIQ RDB boards configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#if defined(CONFIG_TARGET_P1020MBG)
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#define CONFIG_BOARDNAME "P1020MBG-PC"
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#define CONFIG_VSC7385_ENET
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#define CONFIG_SLIC
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#define __SW_BOOT_MASK 0x03
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#define __SW_BOOT_NOR 0xe4
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#define __SW_BOOT_SD 0x54
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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#endif
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#if defined(CONFIG_TARGET_P1020UTM)
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#define CONFIG_BOARDNAME "P1020UTM-PC"
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#define __SW_BOOT_MASK 0x03
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#define __SW_BOOT_NOR 0xe0
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#define __SW_BOOT_SD 0x50
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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#endif
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#if defined(CONFIG_TARGET_P1020RDB_PC)
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#define CONFIG_BOARDNAME "P1020RDB-PC"
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#define CONFIG_NAND_FSL_ELBC
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#define CONFIG_VSC7385_ENET
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#define CONFIG_SLIC
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#define __SW_BOOT_MASK 0x03
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#define __SW_BOOT_NOR 0x5c
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#define __SW_BOOT_SPI 0x1c
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#define __SW_BOOT_SD 0x9c
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#define __SW_BOOT_NAND 0xec
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#define __SW_BOOT_PCIE 0x6c
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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#endif
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/*
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* P1020RDB-PD board has user selectable switches for evaluating different
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* frequency and boot options for the P1020 device. The table that
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* follow describe the available options. The front six binary number was in
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* accordance with SW3[1:6].
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* 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
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* 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
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* 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
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* 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
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* 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
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* 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
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* 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
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*/
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#if defined(CONFIG_TARGET_P1020RDB_PD)
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#define CONFIG_BOARDNAME "P1020RDB-PD"
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#define CONFIG_NAND_FSL_ELBC
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#define CONFIG_VSC7385_ENET
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#define CONFIG_SLIC
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#define __SW_BOOT_MASK 0x03
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#define __SW_BOOT_NOR 0x64
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#define __SW_BOOT_SPI 0x34
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#define __SW_BOOT_SD 0x24
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#define __SW_BOOT_NAND 0x44
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#define __SW_BOOT_PCIE 0x74
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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/*
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* Dynamic MTD Partition support with mtdparts
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*/
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#define CONFIG_FLASH_CFI_MTD
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#define MTDIDS_DEFAULT "nor0=ec000000.nor"
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#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \
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"57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
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#endif
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#if defined(CONFIG_TARGET_P1021RDB)
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#define CONFIG_BOARDNAME "P1021RDB-PC"
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#define CONFIG_NAND_FSL_ELBC
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#define CONFIG_QE
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#define CONFIG_VSC7385_ENET
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#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
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addresses in the LBC */
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#define __SW_BOOT_MASK 0x03
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#define __SW_BOOT_NOR 0x5c
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#define __SW_BOOT_SPI 0x1c
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#define __SW_BOOT_SD 0x9c
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#define __SW_BOOT_NAND 0xec
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#define __SW_BOOT_PCIE 0x6c
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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/*
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* Dynamic MTD Partition support with mtdparts
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*/
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#define CONFIG_FLASH_CFI_MTD
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#ifdef CONFIG_PHYS_64BIT
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#define MTDIDS_DEFAULT "nor0=fef000000.nor"
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#define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
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"256k(dtb),4608k(kernel),9728k(fs)," \
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"256k(qe-ucode-firmware),1280k(u-boot)"
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#else
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#define MTDIDS_DEFAULT "nor0=ef000000.nor"
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#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
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"256k(dtb),4608k(kernel),9728k(fs)," \
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"256k(qe-ucode-firmware),1280k(u-boot)"
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#endif
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#endif
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#if defined(CONFIG_TARGET_P1024RDB)
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#define CONFIG_BOARDNAME "P1024RDB"
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#define CONFIG_NAND_FSL_ELBC
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#define CONFIG_SLIC
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#define __SW_BOOT_MASK 0xf3
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#define __SW_BOOT_NOR 0x00
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#define __SW_BOOT_SPI 0x08
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#define __SW_BOOT_SD 0x04
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#define __SW_BOOT_NAND 0x0c
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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#endif
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#if defined(CONFIG_TARGET_P1025RDB)
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#define CONFIG_BOARDNAME "P1025RDB"
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#define CONFIG_NAND_FSL_ELBC
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#define CONFIG_QE
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#define CONFIG_SLIC
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#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
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addresses in the LBC */
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#define __SW_BOOT_MASK 0xf3
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#define __SW_BOOT_NOR 0x00
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#define __SW_BOOT_SPI 0x08
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#define __SW_BOOT_SD 0x04
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#define __SW_BOOT_NAND 0x0c
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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#endif
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#if defined(CONFIG_TARGET_P2020RDB)
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#define CONFIG_BOARDNAME "P2020RDB-PC"
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#define CONFIG_NAND_FSL_ELBC
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#define CONFIG_VSC7385_ENET
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#define __SW_BOOT_MASK 0x03
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#define __SW_BOOT_NOR 0xc8
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#define __SW_BOOT_SPI 0x28
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#define __SW_BOOT_SD 0x68 /* or 0x18 */
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#define __SW_BOOT_NAND 0xe8
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#define __SW_BOOT_PCIE 0xa8
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#define CONFIG_SYS_L2_SIZE (512 << 10)
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/*
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* Dynamic MTD Partition support with mtdparts
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*/
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#define CONFIG_FLASH_CFI_MTD
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#ifdef CONFIG_PHYS_64BIT
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#define MTDIDS_DEFAULT "nor0=fef000000.nor"
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#define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
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"256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
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#else
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#define MTDIDS_DEFAULT "nor0=ef000000.nor"
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#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
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"256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
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#endif
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#endif
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#ifdef CONFIG_SDCARD
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#define CONFIG_SPL_MMC_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#define CONFIG_SPL_TEXT_BASE 0xf8f81000
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#define CONFIG_SPL_PAD_TO 0x20000
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#define CONFIG_SPL_MAX_SIZE (128 * 1024)
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#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
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#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
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#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
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#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
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#define CONFIG_SYS_MPC85XX_NO_RESETVEC
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
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#define CONFIG_SPL_MMC_BOOT
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_COMMON_INIT_DDR
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#endif
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#endif
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#ifdef CONFIG_SPIFLASH
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#define CONFIG_SPL_SPI_FLASH_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#define CONFIG_SPL_TEXT_BASE 0xf8f81000
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#define CONFIG_SPL_PAD_TO 0x20000
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#define CONFIG_SPL_MAX_SIZE (128 * 1024)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
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#define CONFIG_SYS_MPC85XX_NO_RESETVEC
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
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#define CONFIG_SPL_SPI_BOOT
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_COMMON_INIT_DDR
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#endif
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#endif
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#ifdef CONFIG_NAND
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#ifdef CONFIG_TPL_BUILD
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#define CONFIG_SPL_NAND_BOOT
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_NAND_INIT
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#define CONFIG_SPL_COMMON_INIT_DDR
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#define CONFIG_SPL_MAX_SIZE (128 << 10)
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#define CONFIG_SPL_TEXT_BASE 0xf8f81000
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#define CONFIG_SYS_MPC85XX_NO_RESETVEC
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
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#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
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#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
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#elif defined(CONFIG_SPL_BUILD)
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#define CONFIG_SPL_INIT_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_TEXT_BASE 0xff800000
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#define CONFIG_SPL_MAX_SIZE 4096
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
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#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
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#endif /* not CONFIG_TPL_BUILD */
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#define CONFIG_SPL_PAD_TO 0x20000
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#define CONFIG_TPL_PAD_TO 0x20000
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
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#endif
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xeff40000
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#endif
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#ifndef CONFIG_SYS_MONITOR_BASE
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
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#else
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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#endif
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#define CONFIG_MP
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#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
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#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SATA_SIL
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#define CONFIG_SYS_SATA_MAX_DEVICE 2
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#define CONFIG_LIBATA
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#define CONFIG_LBA48
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#if defined(CONFIG_TARGET_P2020RDB)
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#define CONFIG_SYS_CLK_FREQ 100000000
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#else
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#define CONFIG_SYS_CLK_FREQ 66666666
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#endif
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#define CONFIG_DDR_CLK_FREQ 66666666
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#define CONFIG_HWCONFIG
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE
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#define CONFIG_BTB
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#define CONFIG_ENABLE_36BIT_PHYS
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_ADDR_MAP 1
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#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
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#endif
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x1fffffff
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#define CONFIG_SYS_CCSRBAR 0xffe00000
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
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SPL code*/
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
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#endif
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/* DDR Setup */
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#define CONFIG_SYS_DDR_RAW_TIMING
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#define CONFIG_DDR_SPD
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#define CONFIG_SYS_SPD_BUS_NUM 1
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#define SPD_EEPROM_ADDRESS 0x52
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#undef CONFIG_FSL_DDR_INTERACTIVE
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#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
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#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
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#define CONFIG_CHIP_SELECTS_PER_CTRL 2
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#else
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#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
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#define CONFIG_CHIP_SELECTS_PER_CTRL 1
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#endif
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#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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/* Default settings for DDR3 */
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#ifndef CONFIG_TARGET_P2020RDB
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
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#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
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#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
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#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
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#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
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#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
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#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
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#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
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#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
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#define CONFIG_SYS_DDR_RCW_1 0x00000000
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#define CONFIG_SYS_DDR_RCW_2 0x00000000
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#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
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#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
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#define CONFIG_SYS_DDR_TIMING_4 0x00220001
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#define CONFIG_SYS_DDR_TIMING_5 0x03402400
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#define CONFIG_SYS_DDR_TIMING_3 0x00020000
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#define CONFIG_SYS_DDR_TIMING_0 0x00330004
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#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
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#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
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#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
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#define CONFIG_SYS_DDR_MODE_1 0x40461520
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#define CONFIG_SYS_DDR_MODE_2 0x8000c000
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#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
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#endif
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#undef CONFIG_CLOCKS_IN_MHZ
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/*
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* Memory map
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*
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* 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
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* 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
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* 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
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* 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
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* (early boot only)
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* 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
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* 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
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* 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
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* 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
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* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
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* 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
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* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
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*/
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/*
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* Local Bus Definitions
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*/
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#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
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#define CONFIG_SYS_FLASH_BASE 0xec000000
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#elif defined(CONFIG_TARGET_P1020UTM)
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
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#define CONFIG_SYS_FLASH_BASE 0xee000000
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#else
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
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#define CONFIG_SYS_FLASH_BASE 0xef000000
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#endif
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
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#else
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#endif
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#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
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| BR_PS_16 | BR_V)
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#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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/* Nand Flash */
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#ifdef CONFIG_NAND_FSL_ELBC
|
|
#define CONFIG_SYS_NAND_BASE 0xff800000
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
|
|
#else
|
|
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
|
#endif
|
|
|
|
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
|
|
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
|
#if defined(CONFIG_TARGET_P1020RDB_PD)
|
|
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
|
|
#else
|
|
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
|
|
#endif
|
|
|
|
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
|
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
|
| BR_PS_8 /* Port Size = 8 bit */ \
|
|
| BR_MS_FCM /* MSEL = FCM */ \
|
|
| BR_V) /* valid */
|
|
#if defined(CONFIG_TARGET_P1020RDB_PD)
|
|
#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
|
|
| OR_FCM_PGS /* Large Page*/ \
|
|
| OR_FCM_CSCT \
|
|
| OR_FCM_CST \
|
|
| OR_FCM_CHT \
|
|
| OR_FCM_SCY_1 \
|
|
| OR_FCM_TRLX \
|
|
| OR_FCM_EHTR)
|
|
#else
|
|
#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
|
|
| OR_FCM_CSCT \
|
|
| OR_FCM_CST \
|
|
| OR_FCM_CHT \
|
|
| OR_FCM_SCY_1 \
|
|
| OR_FCM_TRLX \
|
|
| OR_FCM_EHTR)
|
|
#endif
|
|
#endif /* CONFIG_NAND_FSL_ELBC */
|
|
|
|
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
|
|
|
|
#define CONFIG_SYS_INIT_RAM_LOCK
|
|
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
|
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
|
|
/* The assembler doesn't like typecast */
|
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
|
|
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
|
|
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
|
|
#else
|
|
/* Initial L1 address */
|
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
|
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
|
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
|
|
#endif
|
|
/* Size of used area in RAM */
|
|
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
|
|
|
|
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
|
GENERATED_GBL_DATA_SIZE)
|
|
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
|
|
|
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
|
|
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
|
|
|
|
#define CONFIG_SYS_CPLD_BASE 0xffa00000
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
|
|
#else
|
|
#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
|
|
#endif
|
|
/* CPLD config size: 1Mb */
|
|
#define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
|
|
BR_PS_8 | BR_V)
|
|
#define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
|
|
|
|
#define CONFIG_SYS_PMC_BASE 0xff980000
|
|
#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
|
|
#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
|
|
BR_PS_8 | BR_V)
|
|
#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
|
|
OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
|
|
OR_GPCM_EAD)
|
|
|
|
#ifdef CONFIG_NAND
|
|
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
|
|
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
|
#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
|
#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
|
#else
|
|
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
|
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
|
#ifdef CONFIG_NAND_FSL_ELBC
|
|
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
|
|
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
|
#endif
|
|
#endif
|
|
#define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
|
|
#define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
|
|
|
|
/* Vsc7385 switch */
|
|
#ifdef CONFIG_VSC7385_ENET
|
|
#define CONFIG_SYS_VSC7385_BASE 0xffb00000
|
|
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
|
|
#else
|
|
#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
|
|
#endif
|
|
|
|
#define CONFIG_SYS_VSC7385_BR_PRELIM \
|
|
(BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
|
|
#define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
|
|
OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
|
|
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
|
|
|
|
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
|
|
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
|
|
|
|
/* The size of the VSC7385 firmware image */
|
|
#define CONFIG_VSC7385_IMAGE_SIZE 8192
|
|
#endif
|
|
|
|
/*
|
|
* Config the L2 Cache as L2 SRAM
|
|
*/
|
|
#if defined(CONFIG_SPL_BUILD)
|
|
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
|
|
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
|
|
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
|
|
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
|
|
#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
|
|
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
|
|
#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
|
|
#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
|
|
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
|
|
#if defined(CONFIG_TARGET_P2020RDB)
|
|
#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
|
|
#else
|
|
#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
|
|
#endif
|
|
#elif defined(CONFIG_NAND)
|
|
#ifdef CONFIG_TPL_BUILD
|
|
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
|
|
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
|
|
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
|
|
#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
|
|
#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
|
|
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
|
|
#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
|
|
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
|
|
#else
|
|
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
|
|
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
|
|
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
|
|
#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
|
|
#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
|
|
#endif /* CONFIG_TPL_BUILD */
|
|
#endif
|
|
#endif
|
|
|
|
/* Serial Port - controlled on board with jumper J8
|
|
* open - index 2
|
|
* shorted - index 1
|
|
*/
|
|
#define CONFIG_CONS_INDEX 1
|
|
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
|
#define CONFIG_SYS_NS16550_SERIAL
|
|
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
|
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
|
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
|
|
#define CONFIG_NS16550_MIN_FUNCTIONS
|
|
#endif
|
|
|
|
#define CONFIG_SYS_BAUDRATE_TABLE \
|
|
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
|
|
|
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
|
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
|
|
|
/* I2C */
|
|
#define CONFIG_SYS_I2C
|
|
#define CONFIG_SYS_I2C_FSL
|
|
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
|
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
|
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
|
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
|
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
|
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
|
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
|
|
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
|
|
#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
|
|
|
|
/*
|
|
* I2C2 EEPROM
|
|
*/
|
|
#undef CONFIG_ID_EEPROM
|
|
|
|
#define CONFIG_RTC_PT7C4338
|
|
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
|
#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
|
|
|
|
/* enable read and write access to EEPROM */
|
|
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
|
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
|
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
|
|
|
/*
|
|
* eSPI - Enhanced SPI
|
|
*/
|
|
#define CONFIG_HARD_SPI
|
|
|
|
#if defined(CONFIG_SPI_FLASH)
|
|
#define CONFIG_SF_DEFAULT_SPEED 10000000
|
|
#define CONFIG_SF_DEFAULT_MODE 0
|
|
#endif
|
|
|
|
#if defined(CONFIG_PCI)
|
|
/*
|
|
* General PCI
|
|
* Memory space is mapped 1-1, but I/O space must start from 0.
|
|
*/
|
|
|
|
/* controller 2, direct to uli, tgtid 2, Base address 9000 */
|
|
#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
|
|
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
|
|
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
|
|
#else
|
|
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
|
|
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
|
|
#endif
|
|
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
|
|
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
|
|
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
|
|
#else
|
|
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
|
|
#endif
|
|
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
|
|
|
|
/* controller 1, Slot 2, tgtid 1, Base address a000 */
|
|
#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
|
|
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
|
|
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
|
|
#else
|
|
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
|
|
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
|
|
#endif
|
|
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
|
|
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
|
|
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
|
|
#else
|
|
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
|
|
#endif
|
|
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
|
|
|
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
|
#endif /* CONFIG_PCI */
|
|
|
|
#if defined(CONFIG_TSEC_ENET)
|
|
#define CONFIG_MII /* MII PHY management */
|
|
#define CONFIG_TSEC1
|
|
#define CONFIG_TSEC1_NAME "eTSEC1"
|
|
#define CONFIG_TSEC2
|
|
#define CONFIG_TSEC2_NAME "eTSEC2"
|
|
#define CONFIG_TSEC3
|
|
#define CONFIG_TSEC3_NAME "eTSEC3"
|
|
|
|
#define TSEC1_PHY_ADDR 2
|
|
#define TSEC2_PHY_ADDR 0
|
|
#define TSEC3_PHY_ADDR 1
|
|
|
|
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
|
|
#define TSEC1_PHYIDX 0
|
|
#define TSEC2_PHYIDX 0
|
|
#define TSEC3_PHYIDX 0
|
|
|
|
#define CONFIG_ETHPRIME "eTSEC1"
|
|
|
|
#define CONFIG_HAS_ETH0
|
|
#define CONFIG_HAS_ETH1
|
|
#define CONFIG_HAS_ETH2
|
|
#endif /* CONFIG_TSEC_ENET */
|
|
|
|
#ifdef CONFIG_QE
|
|
/* QE microcode/firmware address */
|
|
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
|
|
#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
|
|
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
|
|
#endif /* CONFIG_QE */
|
|
|
|
#ifdef CONFIG_TARGET_P1025RDB
|
|
/*
|
|
* QE UEC ethernet configuration
|
|
*/
|
|
#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
|
|
|
|
#undef CONFIG_UEC_ETH
|
|
#define CONFIG_PHY_MODE_NEED_CHANGE
|
|
|
|
#define CONFIG_UEC_ETH1 /* ETH1 */
|
|
#define CONFIG_HAS_ETH0
|
|
|
|
#ifdef CONFIG_UEC_ETH1
|
|
#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
|
|
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
|
|
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
|
|
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
|
|
#define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
|
|
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
|
|
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
|
|
#endif /* CONFIG_UEC_ETH1 */
|
|
|
|
#define CONFIG_UEC_ETH5 /* ETH5 */
|
|
#define CONFIG_HAS_ETH1
|
|
|
|
#ifdef CONFIG_UEC_ETH5
|
|
#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
|
|
#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
|
|
#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
|
|
#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
|
|
#define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
|
|
#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
|
|
#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
|
|
#endif /* CONFIG_UEC_ETH5 */
|
|
#endif /* CONFIG_TARGET_P1025RDB */
|
|
|
|
/*
|
|
* Environment
|
|
*/
|
|
#ifdef CONFIG_SPIFLASH
|
|
#define CONFIG_ENV_SPI_BUS 0
|
|
#define CONFIG_ENV_SPI_CS 0
|
|
#define CONFIG_ENV_SPI_MAX_HZ 10000000
|
|
#define CONFIG_ENV_SPI_MODE 0
|
|
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
|
|
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
|
|
#define CONFIG_ENV_SECT_SIZE 0x10000
|
|
#elif defined(CONFIG_SDCARD)
|
|
#define CONFIG_FSL_FIXED_MMC_LOCATION
|
|
#define CONFIG_ENV_SIZE 0x2000
|
|
#define CONFIG_SYS_MMC_ENV_DEV 0
|
|
#elif defined(CONFIG_NAND)
|
|
#ifdef CONFIG_TPL_BUILD
|
|
#define CONFIG_ENV_SIZE 0x2000
|
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
|
|
#else
|
|
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
|
#endif
|
|
#define CONFIG_ENV_OFFSET (1024 * 1024)
|
|
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
|
|
#elif defined(CONFIG_SYS_RAMBOOT)
|
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
|
|
#define CONFIG_ENV_SIZE 0x2000
|
|
#else
|
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
|
#define CONFIG_ENV_SIZE 0x2000
|
|
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
|
#endif
|
|
|
|
#define CONFIG_LOADS_ECHO /* echo on for serial download */
|
|
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
|
|
|
|
/*
|
|
* USB
|
|
*/
|
|
#define CONFIG_HAS_FSL_DR_USB
|
|
|
|
#if defined(CONFIG_HAS_FSL_DR_USB)
|
|
#ifdef CONFIG_USB_EHCI_HCD
|
|
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
|
#define CONFIG_USB_EHCI_FSL
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(CONFIG_TARGET_P1020RDB_PD)
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
|
#endif
|
|
|
|
#ifdef CONFIG_MMC
|
|
#define CONFIG_FSL_ESDHC
|
|
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
|
|
#endif
|
|
|
|
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
|
|
|
/*
|
|
* Miscellaneous configurable options
|
|
*/
|
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
|
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
|
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
|
|
|
/*
|
|
* For booting Linux, the board info and command line data
|
|
* have to be in the first 64 MB of memory, since this is
|
|
* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#endif
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/*
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* Environment Configuration
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*/
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#define CONFIG_HOSTNAME unknown
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#define CONFIG_ROOTPATH "/opt/nfsroot"
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 1000000
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#ifdef __SW_BOOT_NOR
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#define __NOR_RST_CMD \
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norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
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i2c mw 18 3 __SW_BOOT_MASK 1; reset
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#endif
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#ifdef __SW_BOOT_SPI
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#define __SPI_RST_CMD \
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spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
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i2c mw 18 3 __SW_BOOT_MASK 1; reset
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#endif
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#ifdef __SW_BOOT_SD
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#define __SD_RST_CMD \
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sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
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i2c mw 18 3 __SW_BOOT_MASK 1; reset
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#endif
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#ifdef __SW_BOOT_NAND
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#define __NAND_RST_CMD \
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nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
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i2c mw 18 3 __SW_BOOT_MASK 1; reset
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#endif
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#ifdef __SW_BOOT_PCIE
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#define __PCIE_RST_CMD \
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pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
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i2c mw 18 3 __SW_BOOT_MASK 1; reset
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
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"loadaddr=1000000\0" \
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"bootfile=uImage\0" \
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"tftpflash=tftpboot $loadaddr $uboot; " \
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"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
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"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
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"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
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"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
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"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
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"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=2000000\0" \
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"ramdiskfile=rootfs.ext2.gz.uboot\0" \
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"fdtaddr=1e00000\0" \
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"bdev=sda1\0" \
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"jffs2nor=mtdblock3\0" \
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"norbootaddr=ef080000\0" \
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"norfdtaddr=ef040000\0" \
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"jffs2nand=mtdblock9\0" \
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"nandbootaddr=100000\0" \
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"nandfdtaddr=80000\0" \
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"ramdisk_size=120000\0" \
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"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
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"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
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__stringify(__NOR_RST_CMD)"\0" \
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__stringify(__SPI_RST_CMD)"\0" \
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__stringify(__SD_RST_CMD)"\0" \
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__stringify(__NAND_RST_CMD)"\0" \
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__stringify(__PCIE_RST_CMD)"\0"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_HDBOOT \
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"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"usb start;" \
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"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
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"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_USB_FAT_BOOT \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs " \
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"ramdisk_size=$ramdisk_size;" \
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"usb start;" \
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|
"fatload usb 0:2 $loadaddr $bootfile;" \
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|
"fatload usb 0:2 $fdtaddr $fdtfile;" \
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|
"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
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|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
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|
|
|
#define CONFIG_USB_EXT2_BOOT \
|
|
"setenv bootargs root=/dev/ram rw " \
|
|
"console=$consoledev,$baudrate $othbootargs " \
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|
"ramdisk_size=$ramdisk_size;" \
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|
"usb start;" \
|
|
"ext2load usb 0:4 $loadaddr $bootfile;" \
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|
"ext2load usb 0:4 $fdtaddr $fdtfile;" \
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|
"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
|
|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
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|
|
|
#define CONFIG_NORBOOT \
|
|
"setenv bootargs root=/dev/$jffs2nor rw " \
|
|
"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
|
|
"bootm $norbootaddr - $norfdtaddr"
|
|
|
|
#define CONFIG_RAMBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/ram rw " \
|
|
"console=$consoledev,$baudrate $othbootargs " \
|
|
"ramdisk_size=$ramdisk_size;" \
|
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
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|
|
#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
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|
|
#endif /* __CONFIG_H */
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