526 lines
16 KiB
C
526 lines
16 KiB
C
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* QorIQ P1 Tower boards configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#if defined(CONFIG_TWR_P1025)
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#define CONFIG_BOARDNAME "TWR-P1025"
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#define CONFIG_PHY_ATHEROS
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#define CONFIG_QE
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#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
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#define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */
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#endif
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#ifdef CONFIG_SDCARD
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#define CONFIG_RAMBOOT_SDCARD
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#define CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_SYS_TEXT_BASE 0x11000000
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#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
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#endif
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xeff40000
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#endif
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#ifndef CONFIG_SYS_MONITOR_BASE
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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#define CONFIG_MP
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#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
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#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SATA_SIL3114
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#define CONFIG_SYS_SATA_MAX_DEVICE 2
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#define CONFIG_LIBATA
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#define CONFIG_LBA48
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#ifndef __ASSEMBLY__
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extern unsigned long get_board_sys_clk(unsigned long dummy);
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#endif
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */
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#define CONFIG_DDR_CLK_FREQ 66666666
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#define CONFIG_HWCONFIG
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE
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#define CONFIG_BTB
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x1fffffff
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#define CONFIG_SYS_CCSRBAR 0xffe00000
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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/* DDR Setup */
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#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
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#define CONFIG_CHIP_SELECTS_PER_CTRL 1
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#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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/* Default settings for DDR3 */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
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#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
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#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
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#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
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#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
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#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
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#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
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#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608
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#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
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#define CONFIG_SYS_DDR_RCW_1 0x00000000
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#define CONFIG_SYS_DDR_RCW_2 0x00000000
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#define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */
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#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
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#define CONFIG_SYS_DDR_TIMING_4 0x00220001
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#define CONFIG_SYS_DDR_TIMING_5 0x03402400
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#define CONFIG_SYS_DDR_TIMING_3 0x00020000
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#define CONFIG_SYS_DDR_TIMING_0 0x00220004
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#define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544
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#define CONFIG_SYS_DDR_TIMING_2 0x0fa880de
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#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
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#define CONFIG_SYS_DDR_MODE_1 0x80461320
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#define CONFIG_SYS_DDR_MODE_2 0x00008000
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#define CONFIG_SYS_DDR_INTERVAL 0x09480000
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/*
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* Memory map
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*
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* 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable
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* 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
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* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
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*
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* Localbus
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* 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable
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* 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
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*
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* 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable
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* 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable
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* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
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*/
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/*
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* Local Bus Definitions
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*/
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
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#define CONFIG_SYS_FLASH_BASE 0xec000000
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
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| BR_PS_16 | BR_V)
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#define CONFIG_FLASH_OR_PRELIM 0xfc0000b1
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#define CONFIG_SYS_SSD_BASE 0xe0000000
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#define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE
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#define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
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BR_PS_16 | BR_V)
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#define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
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OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
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OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
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#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
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#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
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/* Initial L1 address */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
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/* Size of used area in RAM */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
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#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
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#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
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/* Serial Port
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* open - index 2
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* shorted - index 1
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*/
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#define CONFIG_CONS_INDEX 1
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
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#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
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/*
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* I2C2 EEPROM
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*/
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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#define CONFIG_SYS_I2C_PCA9555_ADDR 0x23
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/* enable read and write access to EEPROM */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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/*
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* eSPI - Enhanced SPI
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*/
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#define CONFIG_HARD_SPI
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#if defined(CONFIG_PCI)
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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/* controller 2, direct to uli, tgtid 2, Base address 9000 */
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#define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT"
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
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#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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/* controller 1, tgtid 1, Base address a000 */
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#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_MII /* MII PHY management */
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#define CONFIG_TSEC1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#undef CONFIG_TSEC2
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#undef CONFIG_TSEC2_NAME
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#define CONFIG_TSEC3
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#define CONFIG_TSEC3_NAME "eTSEC3"
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 0
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#define TSEC3_PHY_ADDR 1
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC3_PHYIDX 0
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#define CONFIG_ETHPRIME "eTSEC1"
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#undef CONFIG_HAS_ETH2
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#endif /* CONFIG_TSEC_ENET */
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#ifdef CONFIG_QE
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/* QE microcode/firmware address */
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#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
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#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
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#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
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#endif /* CONFIG_QE */
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#ifdef CONFIG_TWR_P1025
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/*
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* QE UEC ethernet configuration
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*/
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#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
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#undef CONFIG_UEC_ETH
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#define CONFIG_PHY_MODE_NEED_CHANGE
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#define CONFIG_UEC_ETH1 /* ETH1 */
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#define CONFIG_HAS_ETH0
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#ifdef CONFIG_UEC_ETH1
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#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
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#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
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#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
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#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
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#define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */
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#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
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#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
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#endif /* CONFIG_UEC_ETH1 */
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#define CONFIG_UEC_ETH5 /* ETH5 */
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#define CONFIG_HAS_ETH1
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#ifdef CONFIG_UEC_ETH5
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#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
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#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
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#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
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#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
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#define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */
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#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
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#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
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#endif /* CONFIG_UEC_ETH5 */
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#endif /* CONFIG_TWR-P1025 */
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/*
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* Dynamic MTD Partition support with mtdparts
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*/
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#define CONFIG_FLASH_CFI_MTD
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#define MTDIDS_DEFAULT "nor0=ec000000.nor"
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#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \
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"256k(dtb),5632k(kernel),57856k(fs)," \
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"256k(qe-ucode-firmware),1280k(u-boot)"
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/*
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* Environment
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*/
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#ifdef CONFIG_SYS_RAMBOOT
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#ifdef CONFIG_RAMBOOT_SDCARD
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#else
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
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#endif
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#else
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
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#endif
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#define CONFIG_LOADS_ECHO /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
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/*
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* USB
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*/
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#define CONFIG_HAS_FSL_DR_USB
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#if defined(CONFIG_HAS_FSL_DR_USB)
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#ifdef CONFIG_USB_EHCI_HCD
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_USB_EHCI_FSL
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#endif
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#endif
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#ifdef CONFIG_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_CMDLINE_EDITING /* Command-line editing */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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/*
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* Environment Configuration
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*/
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#define CONFIG_HOSTNAME unknown
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#define CONFIG_ROOTPATH "/opt/nfsroot"
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 1000000
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
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"loadaddr=1000000\0" \
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"bootfile=uImage\0" \
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"dtbfile=twr-p1025twr.dtb\0" \
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"ramdiskfile=rootfs.ext2.gz.uboot\0" \
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"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \
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"tftpflash=tftpboot $loadaddr $uboot; " \
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"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
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"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
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"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
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"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
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"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
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"kernelflash=tftpboot $loadaddr $bootfile; " \
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"protect off 0xefa80000 +$filesize; " \
|
|
"erase 0xefa80000 +$filesize; " \
|
|
"cp.b $loadaddr 0xefa80000 $filesize; " \
|
|
"protect on 0xefa80000 +$filesize; " \
|
|
"cmp.b $loadaddr 0xefa80000 $filesize\0" \
|
|
"dtbflash=tftpboot $loadaddr $dtbfile; " \
|
|
"protect off 0xefe80000 +$filesize; " \
|
|
"erase 0xefe80000 +$filesize; " \
|
|
"cp.b $loadaddr 0xefe80000 $filesize; " \
|
|
"protect on 0xefe80000 +$filesize; " \
|
|
"cmp.b $loadaddr 0xefe80000 $filesize\0" \
|
|
"ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \
|
|
"protect off 0xeeb80000 +$filesize; " \
|
|
"erase 0xeeb80000 +$filesize; " \
|
|
"cp.b $loadaddr 0xeeb80000 $filesize; " \
|
|
"protect on 0xeeb80000 +$filesize; " \
|
|
"cmp.b $loadaddr 0xeeb80000 $filesize\0" \
|
|
"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \
|
|
"protect off 0xefec0000 +$filesize; " \
|
|
"erase 0xefec0000 +$filesize; " \
|
|
"cp.b $loadaddr 0xefec0000 $filesize; " \
|
|
"protect on 0xefec0000 +$filesize; " \
|
|
"cmp.b $loadaddr 0xefec0000 $filesize\0" \
|
|
"consoledev=ttyS0\0" \
|
|
"ramdiskaddr=2000000\0" \
|
|
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
|
|
"fdtaddr=1e00000\0" \
|
|
"bdev=sda1\0" \
|
|
"norbootaddr=ef080000\0" \
|
|
"norfdtaddr=ef040000\0" \
|
|
"ramdisk_size=120000\0" \
|
|
"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
|
|
"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
|
|
|
|
#define CONFIG_NFSBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/nfs rw " \
|
|
"nfsroot=$serverip:$rootpath " \
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp $loadaddr $bootfile&&" \
|
|
"tftp $fdtaddr $fdtfile&&" \
|
|
"bootm $loadaddr - $fdtaddr"
|
|
|
|
#define CONFIG_HDBOOT \
|
|
"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"usb start;" \
|
|
"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
|
|
"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
|
|
"bootm $loadaddr - $fdtaddr"
|
|
|
|
#define CONFIG_USB_FAT_BOOT \
|
|
"setenv bootargs root=/dev/ram rw " \
|
|
"console=$consoledev,$baudrate $othbootargs " \
|
|
"ramdisk_size=$ramdisk_size;" \
|
|
"usb start;" \
|
|
"fatload usb 0:2 $loadaddr $bootfile;" \
|
|
"fatload usb 0:2 $fdtaddr $fdtfile;" \
|
|
"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
|
|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
|
|
|
#define CONFIG_USB_EXT2_BOOT \
|
|
"setenv bootargs root=/dev/ram rw " \
|
|
"console=$consoledev,$baudrate $othbootargs " \
|
|
"ramdisk_size=$ramdisk_size;" \
|
|
"usb start;" \
|
|
"ext2load usb 0:4 $loadaddr $bootfile;" \
|
|
"ext2load usb 0:4 $fdtaddr $fdtfile;" \
|
|
"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
|
|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
|
|
|
#define CONFIG_NORBOOT \
|
|
"setenv bootargs root=/dev/mtdblock3 rw " \
|
|
"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
|
|
"bootm $norbootaddr - $norfdtaddr"
|
|
|
|
#define CONFIG_RAMBOOTCOMMAND_TFTP \
|
|
"setenv bootargs root=/dev/ram rw " \
|
|
"console=$consoledev,$baudrate $othbootargs " \
|
|
"ramdisk_size=$ramdisk_size;" \
|
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
|
|
|
#define CONFIG_RAMBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/ram rw " \
|
|
"console=$consoledev,$baudrate $othbootargs " \
|
|
"ramdisk_size=$ramdisk_size;" \
|
|
"bootm 0xefa80000 0xeeb80000 0xefe80000"
|
|
|
|
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
|
|
|
|
#endif /* __CONFIG_H */
|