42 lines
		
	
	
		
			1.1 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			42 lines
		
	
	
		
			1.1 KiB
		
	
	
	
		
			C
		
	
	
	
| /* SPDX-License-Identifier: GPL-2.0+ */
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| /*
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|  * Configuration file for the SAMA5D2 PTC EK Board.
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|  *
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|  * Copyright (C) 2017 Microchip Technology Inc.
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|  *		      Wenyou Yang <wenyou.yang@microchip.com>
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|  *		      Ludovic Desroches <ludovic.desroches@microchip.com>
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|  */
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| 
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| #ifndef __CONFIG_H
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| #define __CONFIG_H
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| 
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| #include "at91-sama5_common.h"
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| 
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| #undef CONFIG_SYS_AT91_MAIN_CLOCK
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| #define CONFIG_SYS_AT91_MAIN_CLOCK      24000000 /* from 24 MHz crystal */
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| 
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| #define CONFIG_MISC_INIT_R
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| 
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| /* SDRAM */
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| #define CONFIG_NR_DRAM_BANKS		1
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| #define CONFIG_SYS_SDRAM_BASE		0x20000000
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| #define CONFIG_SYS_SDRAM_SIZE		0x20000000
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| 
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| #define CONFIG_SYS_INIT_SP_ADDR \
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| 	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
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| 
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| #define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
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| 
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| /* NAND Flash */
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| #ifdef CONFIG_CMD_NAND
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| #define CONFIG_SYS_MAX_NAND_DEVICE	1
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| #define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
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| /* our ALE is AD21 */
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| #define CONFIG_SYS_NAND_MASK_ALE	BIT(21)
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| /* our CLE is AD22 */
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| #define CONFIG_SYS_NAND_MASK_CLE	BIT(22)
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| #define CONFIG_SYS_NAND_ONFI_DETECTION
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| #endif
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| 
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| #endif /* __CONFIG_H */
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