54 lines
		
	
	
		
			1.0 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			54 lines
		
	
	
		
			1.0 KiB
		
	
	
	
		
			C
		
	
	
	
| /*
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|  *  Copyright (C) 2015-2017 Altera Corporation <www.altera.com>
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0
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|  */
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| 
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| #ifndef __CONFIG_SOCFGPA_ARRIA10_H__
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| #define __CONFIG_SOCFGPA_ARRIA10_H__
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| 
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| #include <asm/arch/base_addr_a10.h>
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| 
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| #define CONFIG_HW_WATCHDOG
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| 
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| /* Booting Linux */
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| #define CONFIG_LOADADDR		0x01000000
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| #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
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| 
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| /*
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|  * U-Boot general configurations
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|  */
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| /* Cache options */
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| #define CONFIG_SYS_DCACHE_OFF
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| 
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| /* Memory configurations  */
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| #define PHYS_SDRAM_1_SIZE		0x40000000
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| 
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| /* Ethernet on SoC (EMAC) */
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| 
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| /*
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|  * U-Boot environment configurations
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|  */
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| 
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| /*
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|  * Serial / UART configurations
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|  */
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| #define CONFIG_SYS_NS16550_MEM32
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| #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
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| 
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| /*
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|  * L4 OSC1 Timer 0
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|  */
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| /* reload value when timer count to zero */
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| #define TIMER_LOAD_VAL			0xFFFFFFFF
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| 
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| /*
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|  * Flash configurations
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|  */
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| #define CONFIG_SYS_MAX_FLASH_BANKS     1
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| 
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| /* The rest of the configuration is shared */
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| #include <configs/socfpga_common.h>
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| 
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| #endif	/* __CONFIG_SOCFGPA_ARRIA10_H__ */
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